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PIC18F2221/2321/4221/4321 FAMILY
DS39689F-page 108
2009 Microchip Technology Inc.
10.5
RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 5.1 “RCON
REGISTER 10-10: RCON: RESET CONTROL REGISTER
R/W-0
R/W-1(1)
U-0
R/W-1
R-1
R/W-0(2)
R/W-0
IPEN
SBOREN
—RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16XXX Compatibility mode)
bit 6
SBOREN: Software BOR Enable bit(1)
For details of bit operation, see Register 5-1.
bit 5
Unimplemented: Read as ‘0’
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 5-1.
bit 3
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 5-1.
bit 2
PD: Power-down Detection Flag bit
For details of bit operation, see Register 5-1.
bit 1
POR: Power-on Reset Status bit(2)
For details of bit operation, see Register 5-1.
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 5-1.
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: Actual Reset values are determined by device configuration and the nature of the
device Reset. See Register 5-1 for additional information.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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